AK5730 Datasheet, PDF (13/50 Pages) Asahi Kasei Microsystems – 4-Channel Differential Audio ADC for Line & Mic Inputs

[AK5730]
Parameter
Symbol
min
typ
max Unit
Control Interface Timing (4-wire serial mode)
CCLK Period
tCCK
200
ns
CCLK Pulse Width Low
tCCKL
80
ns
Pulse Width High
tCCKH
80
ns
CDTI Setup Time
tCDS
50
ns
CDTI Hold Time
tCDH
50
ns
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSW
150
ns
tCSS
50
ns
tCSH
50
ns
CDTO Delay
CSN “↑” to CDTO Hi-Z
Control Interface Timing (I²C Bus):
tDCD
tCCZ
45
ns
70
ns
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU :STA
0.6
SDA Hold Time from SCL Falling
(Note 19)
tHD :DAT
0
SDA Setup Time from SCL Rising
tSU :DAT 0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter tSP :I²C
0
400 kHz
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
1.0
μs
0.3
μs
-
μs
50
ns
Capacitive load on bus
Cb
-
400
pF
Power-down & Reset Timing
PDN Pulse Width
(Note 20)
tPD
150
ns
PDN “↑” to SDTO valid (FS1/0bit=“00”) (Note 21)
tPDV
3153
1/fs
PDN “↑” to SDTO valid (FS1/0bit=“01”) (Note 21)
2098
1/fs
PDN “↑” to SDTO valid (FS1/0bit=“10”) (Note 21)
1729
1/fs
Pulse Width of Spike Noise Suppressed by Input Filter tSP :PD
0
20
ns
Note 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 20. The AK5730 can be reset by setting the PDN pin to “L” upon power-up.
Note 21. These cycles are the numbers of LRCK rising from the PDN pin rising.
Note 22. I²C-bus is a trademark of NXP B.V.
Rev 0.8
- 13 -
2013/06