AK5730 Datasheet, PDF (36/50 Pages) Asahi Kasei Microsystems – 4-Channel Differential Audio ADC for Line & Mic Inputs

[AK5730]
Notes:
(1) The PDN pin should be set to “H” after all powers (DVDD, AVDD) are supplied. The AK5730 requires 150ns or
longer “L” period for a certain reset. Supply the power during the PDN pin = “L”.
(2) Set RSTN bit to “1” after setting microphone bias voltage (MBS3-0 bits).
(3) Power-on the PLL circuit:(PLL mode)
PLL1-0 bits = “01” or “10” or “11” & BICK is input.
PLL is locked within 1 - 2ms
(4) Power-on the MICREF circuit:
The CVP1 pin is charged up.
The MICREF pin becomes (1.67 x VDD) x 2 within about 20 - 40ms.
(5) ADC outputs “0” data in power-down state.
(6) Power-on the charge pump circuit1/2:
(Normal mode) PDN pin = “L” → “H”(or PLL is locked) & MCLK, BICK, LRCK is input.(normal mode)
(PLL mode) PLL is locked.
The CVP1 pin becomes 1.67 x VDD within about 4 - 8ms.
The CVP2 pin becomes (1.67 x VDD) x 2 within about 4 - 8ms.
(7) The analog block of ADC is initialized after exiting the power-down state.
(8) Digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group
delay (GD).
(9) Charge pump circuit power down:
PDN pin = “H” Æ “L”
The CVP1/2 pin becomes VDD according to a flying capacitor and internal resistor. The internal resistor is 50kΩ
(typ). Therefore, when the CVP1/2 pin has a flying capacitor of 2.2µF, the time constant is 110ms (typ).
Rev 0.8
- 36 -
2013/06