AK5730 Datasheet, PDF (37/50 Pages) Asahi Kasei Microsystems – 4-Channel Differential Audio ADC for Line & Mic Inputs

[AK5730]
■ Serial Control Interface
(1) 4-wire Serial Control Mode (SPI pin = “H”)
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO.
The data on this interface consists of Chip address (1bit, C1 is fixed to “1”), Read/Write (1bit), Register address
(MSB first, 6bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK
and data is clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK,
after a high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a
low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. The PDN pin= “L” resets the registers to
their default values.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
WRITE
CDTO
READ
CDTI
CDTO
C1 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
C1 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
C1: Chip Address (Fixed to “1”)
R/W: READ/WRITE (0:READ, 1:WRITE)
A5-A0: Register Address
D7-D0: Control Data
Figure 35. 4-wire Serial Control I/F Timing
(2). I²C bus control mode (SPI pin = “L”)
The AK5730 supports the fast-mode I²C-bus (max: 400kHz).
(2)-1. WRITE Operations
Figure 36 shows the data transfer sequence of the I²C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 42). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant five bits of the slave address are fixed as “00100”. The next bits are CAD1 and CAD0
(device address bit). This bit identifies the specific device on the bus. The hard-wired input pins (CAD1/0 pins) set these
device address bits (Figure 37). If the slave address matches that of the AK5730, the AK5730 generates an acknowledge
and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line
(HIGH) during the acknowledge clock pulse (Figure 43). R/W bit = “1” indicates that the read operation is to be executed.
“0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK5730. The format is MSB first, and those most
significant 2-bits are fixed to zeros (Figure 38). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 39). The AK5730 generates an acknowledge after each byte is received. Data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition (Figure 42).
The AK5730 can perform more than one byte write operation per sequence. After receipt of the third byte the AK5730
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
Rev 0.8
- 37 -
2013/06