AK4569 Datasheet, PDF (32/45 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with IPGA & HP-AMP

ASAHI KASEI
[AK4569]
Addr Register Name
04H ALC Mode Control 2
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
REF6 REF5 REF4 REF3 REF2 REF1 REF0
0
0
1
1
1
1
1
1
REF6-0: Reference Value at ALC Recovery Operation, 0.5dB step, 103 levels, Default: “3FH” (Table 12)
During the ALC recovery operation, if the IPGA value exceeds the set reference value by gain operation,
IPGA does not become larger than the reference value. For example, when REF= “40H”, RATT= “1” (2
step) and IPGA= “3FH”, then IPGA is going to become 3FH + 2step = 41H, but IPGA becomes 40H in
fact, since REF=40H.
GAIN
DATA _{AINL1, AINR1 AINL2, AINR2}
(LINE IN)
(MIC IN)
67H
+20.0dB
+32.0dB
66H
+19.5dB
+31.5dB
65H
+19.0dB
+31.0dB
:
:
:
3FH
0dB
+12.0dB
Default
:
:
:
27H
−12.0dB
0dB
:
:
:
02H
−30.5dB
−18.5dB
01H
−31.0dB
−19.0dB
00H
MUTE (−∞)
MUTE (−∞)
Table 12. Reference Value Setting at ALC Recovery Operation
Addr Register Name
05H IPGA Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
IPGA6 IPGA5 IPGA4 IPGA3 IPGA2 IPGA1 IPGA0
0
0
1
1
1
1
1
1
IPGA6-0: Input Analog PGA, 0.5dB step, 103 levels, Default: “3FH” (Table 13)
When IPGA gain is changed, IPGA6-0 bits should be written while PMADC bit is “1” and ALC bit is “0”.
IPGA gain is reset when PMADC bit is “0”, and then IPGA operation starts from the default value when
PMADC is changed to “1”. When ALC bit is changed from “1” to “0”, IPGA holds the last gain value set
by ALC operation.
DATA
67H
66H
65H
:
3FH
:
27H
:
02H
01H
00H
GAIN
AINL1, AINR1 AINL2, AINR2
(LINE IN)
(MIC IN)
+20.0dB
+19.5dB
+19.0dB
:
0dB
:
−12.0dB
:
−30.5dB
−31.0dB
+32.0dB
+31.5dB
+31.0dB
:
+12.0dB
:
0dB
:
−18.5dB
−19.0dB
MUTE (−∞)
MUTE (−∞)
Table 13. Input Gain Setting
Default
MS0292-E-01
- 32 -
2005/07