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AK4569 Datasheet, PDF (24/45 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with IPGA & HP-AMP | |||
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ASAHI KASEI
[AK4569]
3) DAC â MOUT
Power Supply
PDN pin
HPLMT,
HPRMT bit
PMVCM bit
Clock Input
(1) >150ns
(2)
>0
(4)
Donât care
Donât care
PMDAC bit
DAC Internal
State
SDTI pin
PMMO bit
ATTL/R7-0 bit
(3) >0
PD(Power-down)
00H(MUTE)
Normal Operation
PD
Normal Operation
FFH(0dB)
00H(MUTE)
FFH(0dB)
MMUTE,
ATTM3-0 bit
MOUT pin
10H(MUTE)
0FH(0dB)
(6) GD (7) 1061/fs (6) (7)
(Hi-Z)
(5)
(5)
(5)
(Hi-Z)
Figure 19. Power-up/down sequence of DAC and MOUT
(6) (7)
(1) PDN pin should be set to âHâ at least 150ns after the power is supplied.
(2) HPLMT, HPRMT and PMVCM bits should be changed to â1â after PDN pin goes to âHâ.
(3) PMDAC and PMMO bits should be changed to â1â after HPLMT, HPRMT and PMVCM bits are changed to â1â.
(4) External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC= â0â, these clocks can be
stopped. MOUT buffer can operate without these clocks.
(5) When PMMO bit is changed to â1â, pop noise is output from MOUT pin.
(6) Analog output corresponding to digital input has the group delay (GD) of 16.8/fs(=381µs@fs=44.1kHz).
(7) ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
MS0292-E-01
- 24 -
2005/07
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