AK4569 Datasheet, PDF (26/45 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with IPGA & HP-AMP

ASAHI KASEI
[AK4569]
„ Serial Control Interface
Internal registers may be written via to the 3 wire µP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of Chip address (2bits, Fixed to “10”), Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK. For write
operations, data is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz(max). The value of
internal registers is initialized at PDN= “L”.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (Fixed to “10”)
R/W:Read/Write (Fixed to “1” : Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 21. Control Interface
MS0292-E-01
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2005/07