AK4569 Datasheet, PDF (10/45 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with IPGA & HP-AMP

ASAHI KASEI
[AK4569]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, HVDD = 2.5 ∼ 3.6V: CL = 20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
fCLK
2.048
24.576
MHz
Pulse Width Low
(Note 20)
tCLKL
0.4/fCLK
ns
Pulse Width High
(Note 20)
tCLKH
0.4/fCLK
ns
AC Pulse Width
(Note 21)
tACW
0.4/fCLK
ns
LRCK Timing
Frequency
fs
8
44.1
48
kHz
Duty Cycle
Duty
45
55
%
Serial Interface Timing (Note 22)
BICK Period
tBCK
325.5
ns
BICK Pulse Width Low
tBCKL
130
ns
Pulse Width High
tBCKH
130
ns
LRCK Edge to BICK “↑” (Note 23)
tLRB
50
BICK “↑” to LRCK Edge (Note 23)
tBLR
50
LRCK to SDTO(MSB)
tLRS
BICK “↓” to SDTO
tBSD
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
ns
ns
80
ns
80
ns
ns
ns
Control Interface Timing
CCLK Period
tCCK
200
ns
CCLK Pulse Width Low
tCCKL
80
ns
Pulse Width High
tCCKH
80
ns
CDTI Setup Time
tCDS
40
ns
CDTI Hold Time
tCDH
40
ns
CSN “H” Time
tCSW
150
ns
CSN “↓” to CCLK “↑”
tCSS
50
ns
CCLK “↑” to CSN “↑”
tCSH
50
ns
Power-down & Reset Timing
PDN Pulse Width
(Note 24)
tPD
150
ns
PMADC “↑” to SDTO valid (Note 25)
tPDV
2081
1/fs
Note 20. Except AC coupling.
Note 21. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to
ground. (Refer to Figure 4.)
Note 22. Refer to “Serial Data Interface”.
Note 23. BICK rising edge must not occur at the same time as LRCK edge.
Note 24. The AK4569 can be reset by bringing PDN= “L” to “H” only upon power up.
Note 25. This is the count of LRCK “↑” from PMADC bit=”1”.
MS0292-E-01
- 10 -
2005/07