AK4569 Datasheet, PDF (14/45 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with IPGA & HP-AMP

ASAHI KASEI
[AK4569]
OPERATION OVERVIEW
„ System Clock
The external clocks required to operate the AK4569 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master
clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter.
The frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency.
Table 1 shows system clock example.
LRCK
fs
8kHz
11.025kHz
12kHz
16kHz
22.05kHz
24kHz
32kHz
44.1kHz
48kHz
MCLK (MHz)
256fs
384fs
512fs
2.048
3.072
4.096
2.8224 4.2336 5.6448
3.072
4.608
6.144
4.096
6.144
8.192
5.6448 8.4672 11.2896
6.144
9.216
12.288
8.192
12.288 16.384
11.2896 16.9344 22.5792
12.288 18.432 24.576
BICK (MHz)
64fs
0.512
0.7056
0.768
1.024
1.4112
1.536
2.048
2.8224
3.072
Table 1. System Clock Example
External clocks (MCLK, BICK and LRCK) are needed to operate ADC or DAC. All external clocks (MCLK, BICK and
LRCK) should always be present whenever the ADC or DAC is in normal operation mode (PMADC bit = “1” or PMDAC
bit = “1”). If these clocks are not provided, the AK4569 may draw excess current and will not operate properly because it
utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, AK4569 should be
placed in power-down mode (PDN pin = “L” or PMADC bit = PMDAC bit = “0”). When MCLK is input with AC
coupling, the MCKAC bit should be set to “1”. If MCLK with AC coupling stops, MCKPD bit should be set to “1”.
For low sampling rates, outband noise causes both DR and S/N to degrade. DR and S/N are improved by setting DFS bit
to “1”. Table 2 shows S/N of DAC output for both the HP-amp and MOUT. When the DFS bit is “1”, MCLK needs 512fs.
During normal operation, when the ADC or DAC sampling frequency is changed (PMADC bit = “1” or PMDAC bit =
“1”), the DAC output should be soft-muted or “0” data should be input to avoid pop noise.
DFS
fs
MCLK
S/N (fs=8kHz, A-weighted)
HP-amp
MOUT
0
8kHz∼48kHz 256fs/384fs/512fs
84dB
84dB
Default
1
8kHz∼24kHz
512fs
90dB
88dB
Table 2. Relationship among fs, MCLK frequency and S/N of HP-amp and MOUT
MS0292-E-01
- 14 -
2005/07