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AK4569 Datasheet, PDF (22/45 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with IPGA & HP-AMP | |||
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ASAHI KASEI
[AK4569]
 Power-Up/Down Sequence
1) ADC
Power Supply
PDN pin
HPLMT,
HPRMT bit
PMVCM bit
Clock Input
PMADC bit
ADC Internal
State
AIN pin
SDTO pin
(1) >150ns
(2)
>0
(4)
Donât care
(3) >0
(6) 2081/fs
Donât care
(6) 2081/fs
PD(Power-down) Init Cycle Normal Operation
PD
(5)
(Hi-Z)
(7) GD
(Hi-Z)
(7) GD
Init Cycle Normal Operation
(7) GD
Figure 17. Power-up/down sequence of ADC
(1) PDN pin should be set to âHâ at least 150ns after the power is supplied.
(2) HPLMT, HPRMT and PMVCM bits should be changed to â1â after PDN pin goes to âHâ.
(3) PMADC bit should be changed to â1â after HPLMT, HPRMT and PMVCM bits are changed to â1â.
(4) External clocks (MCLK, BICK, LRCK) are needed to operate ADC.
(5) When PMADC bit is changed to â1â, each AIN pin is biased to VCOM voltage. Rising time constant is determined
by input capacitor for AC coupling and input resistance. In case of AINL2/AINR2 and 1µF input capacitor, time
constant is
Ï = 1µF x 12.5k⦠= 12.5ms (typ)
(6) The analog part of ADC is initialized during 2081/fs(=47ms@fs=44.1kHz) after exiting the power-down state.
SDTO is âLâ at that time.
(7) Digital output corresponding to analog input has the group delay (GD) of 17.0/fs(=385µs@fs=44.1kHz).
MS0292-E-01
- 22 -
2005/07
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