AK4569 Datasheet, PDF (19/45 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with IPGA & HP-AMP

ASAHI KASEI
[AK4569]
„ IPGA Operation
[Write Operation at ALC Enabled]
The values of IPGA6-0 bits are ignored during ALC operation.
[Write Operation at ALC Disabled]
Channel independent zero crossing detection is used. If there are no zero crossings, then the level will change after a
timeout. The ZTM1-0 bits set the zero crossing timeout. When a µP writes to the IPGA6-0 bits, the zero crossing counter
is reset and starts. When the IPGA output signal detects zero crossing or a zero crossing timeout, the written value from
the µP becomes valid.
When writing to the IPGA6-0 bits continually, the control register should be written by an interval
more than zero crossing timeout. If not, there is a possibility that each IPGA of L/R channels has a different gain.
[IPGA Gain after completing ALC operation]
The IPGA6-0 bits are not updated by the actual gain of IPGA changed during ALC operation. In order to set the actual
gain of IPGA with the IPGA6-0 bits, the IPGA6-0 bits should be written after zero crossing timeout period when
completing ALC operation (ALC bit= “1” Æ “0”).
MS0292-E-01
- 19 -
2005/07