AK4390 Datasheet, PDF (28/32 Pages) Asahi Kasei Microsystems – Ultra Low Latency 32-Bit ΔΣ DAC

[AK4390]
Digital Ground
System
Controller
Analog Ground
1 SMUTE/CSN
LRCK 30
2 TST1/CAD0
SDATA 29
3 DEM0/CCLK
BICK 28
4 DEM1/CDTI
PDN 27
5 DIF0/CAD1
DVDD 26
6 DIF1/DZFL
VSS4 25
7 DIF2
8 PSN
AK4390 ^{MCLK 24}
AVDD 23
9 ^TST2/DZFR
VSS3 22
10 ^AOUTRP
AOUTLP 21
11 AOUTRN
AOUTLN 20
12 VSS1
VSS2 19
13 VDRR
VDDL 18
14 VREFHR
VREFHL 17
15 VREFLR
VREFLL 16
Figure 13. Ground Layout
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively.
AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. Power lines of
AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc. The power up
sequence between AVDD and DVDD is not critical. VSS1/2/3/4 must be connected to the same analog ground
plane. Decoupling capacitors for high frequency should be placed as near as possible to the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the analog output range. The VREFHL/R pin is
normally connected to AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R and VREFLL/R
should be connected with a 0.1µF ceramic capacitor. All signals, especially clocks, should be kept away from the
VREFHL/R and VREFLL/R pins in order to avoid unwanted noise coupling into the AK4390.
3. Analog Outputs
The analog outputs are fully differential outputs at 2.8Vpp (typ, VREFHL/R − VREFLL/R = 5V), centered around
AVDD/2 (typ). The differential outputs are summed externally, V_AOUT = (AOUT+) − (AOUT−) between AOUT+ and
AOUT−. If the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R − VREFLL/R = 5V). The bias voltage of
the external summing circuit is supplied externally. The input data format is two’s complement. The output voltage
(V_AOUT) is positive full scale for 7FFFFFH (@24-bits) and negative full scale for 800000H (@24-bits). The ideal V_AOUT
is 0V for 000000H(@24-bits).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband. Figure 14 shows an example of an external LPF circuit summing the differential outputs with an op-amp.
Figure 15 shows an example of differential outputs and a LPF circuit example by three op-amps.
MS1046-E-00
- 28 -
2009/01