AK4390 Datasheet, PDF (11/32 Pages) Asahi Kasei Microsystems – Ultra Low Latency 32-Bit ΔΣ DAC

[AK4390]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)
Parameter
Symbol
min
typ
Master Clock Timing
Frequency
fCLK
7.7
Duty Cycle
dCLK
40
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
(Note 16)
fsn
30
fsd
30
fsq
108
Duty
45
PCM Audio Interface Timing
BICK Period
Normal Speed Mode
tBCK
1/128fn
Double Speed Mode
tBCK
1/64fd
Quad Speed Mode
tBCK
1/64fq
BICK Pulse Width Low
tBCKL
30
BICK Pulse Width High
tBCKH
30
BICK “↑” to LRCK Edge
(Note 17) tBLR
20
LRCK Edge to BICK “↑”
(Note 17) tLRB
20
SDATA Hold Time
tSDH
20
SDATA Setup Time
tSDS
20
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
50
CDTI Hold Time
tCDH
50
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSW
150
tCSS
50
tCSH
50
Reset Timing
PDN Pulse Width
(Note 18) tPD
150
max
41.472
60
54
108
216
55
Units
MHz
%
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 16. When the frequency (1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs) is switched, the AK4390 should be
reset by the PDN pin or RSTN bit.
Note 17. BICK rising edge must not occur at the same time as LRCK edge.
Note 18. The AK4390 can be reset by bringing the PDN pin “L” to “H”.
MS1046-E-00
- 11 -
2009/01