AK4390 Datasheet, PDF (24/32 Pages) Asahi Kasei Microsystems – Ultra Low Latency 32-Bit ΔΣ DAC

[AK4390]
■ Register Map
Addr
00H
01H
02H
03H
04H
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
D7
0
DZFE
0
ATT7
ATT7
D6
0
DZFM
0
ATT6
ATT6
D5
0
SD
0
ATT5
ATT5
D4
0
DFS1
0
ATT4
ATT4
D3
DIF2
DFS0
0
ATT3
ATT3
D2
DIF1
DEM1
DZFB
ATT2
ATT2
D1
DIF0
DEM0
0
ATT1
ATT1
D0
RSTN
SMUTE
0
ATT0
ATT0
Notes:
Data must not be written into addresses from 05H to 1FH.
When the PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default
values.
When the state of the PSN pin is changed, the AK4390 should be reset by the PDN pin.
■ Register Definitions
Addr Register Name
00H Control 1
Default
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
DIF2
DIF1
DIF0
0
0
0
0
0
1
0
RSTN: Internal timing reset
0: Reset. All registers are not initialized.
1: Normal Operation (default)
When internal clocks are changed, the AK4390 should be reset by the PDN pin or RSTN bit.
DIF2-0: Audio data interface modes (Table 4)
Initial value is “010” (Mode 2: 24-bit MSB justified).
D0
RSTN
1
MS1046-E-00
- 24 -
2009/01