|
AK4390 Datasheet, PDF (19/32 Pages) Asahi Kasei Microsystems – Ultra Low Latency 32-Bit ΔΣ DAC | |||
|
◁ |
[AK4390]
â Power ON/OFF timing
The AK4390 is placed in the power-down mode by bringing the PDN pin âLâ and the registers are initialized. the analog
outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN pin signal, the analog output should be
muted externally if the click noise influences system application.
The DAC can be reset by setting RSTN bit to â0â. In this case, the registers are not initialized and the corresponding
analog outputs go to AVDD/2 (typ). As some click noise occurs at the edge of RSTN signal, the analog output should be
muted externally if click noise aversely affect system performance.
Power
PDN pin
(1)
Internal
State
Normal Operation
DAC In
(Digital)
â0âdata
DAC Out
(Analog)
(3)
(4)
Clock In
Donât care
MCLK,LRCK,BICK
DZFL/DZFR
External
Mute
(6)
Mute ON
GD (2)
Reset
â0âdata
GD
(4)
(3)
(5)
Donât care
(7)
Mute ON
Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be âLâ for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) Analog outputs are floating (Hi-Z) in power-down mode.
(4) Click noise occurs at the edge of PDN signal. This noise is output even if â0â data is input.
(5) Mute the analog output externally if click noise (3) adversely affect system performance
The timing example is shown in this figure.
(6) DZFL/R pins are âLâ in the power-down mode (PDN pin = âLâ). (DZFB bit = â0â)
Figure 8. Power-down/up Sequence Example
MS1046-E-00
- 19 -
2009/01
|
▷ |