AK4390 Datasheet, PDF (20/32 Pages) Asahi Kasei Microsystems – Ultra Low Latency 32-Bit ΔΣ DAC

[AK4390]
■ Reset Function
(1) RESET by RSTN bit = “0”
When the RSTN bit = “0”, the AK4390’s digital section is powered down, but the internal register values are not
initialized. The analog outputs settle to AVDD/2 (typ) and the DZF pins for both channels go to “H”. Figure 9 shows the
example of reset by RSTN bit.
RSTN bit
In ternal
RSTN bit
3~4/fs (5)
2~3/fs (5)
In ternal
Stat e
D/A In
(Dig ital )
D/A Out
(Ana log )
DZF
Normal Operation
(1)
GD
D igital Block
P
d
“0 ” data
(3) (2)
Normal O peration
GD (1)
(3)
2/ fs(4)
(6)
Notes:
(1) The analog output corresponding to digital input has group delay (GD).
(2) Analog outputs settle to AVDD/2 (typ).
(3) Click noise occurs at the edges (“↑ ↓”) of the internal timing of RSTN bit.
This noise is output even if “0” data is input.
(4) DZF pins go to “H” when the RSTN bit is set to “0”, and return to “L” at 2/fs after the RSTN bit
becomes “1”.
(5) There is a delay, 3 ~ 4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2 ~ 3/fs from RSTN bit “1”
to the internal RSTN bit “1”.
(6) Mute the analog output externally if click noise (3) adversely affect system performance
Figure 9. Reset Sequence Example 1
MS1046-E-00
- 20 -
2009/01