AK4390 Datasheet, PDF (27/32 Pages) Asahi Kasei Microsystems – Ultra Low Latency 32-Bit ΔΣ DAC

[AK4390]
SYSTEM DESIGN
Figure 12 shows the system connection diagram. Figure 14 and Figure 15 shows the analog output circuit examples. The
evaluation board (AKD4390) demonstrates the optimum layout, power supply arrangements and measurement results.
Digital 5.0V
Micro-
Controller
Rch Out
Rch
Mute
1 CSN
2 CAD0
3 CCLK
4 CDTI
5 CAD1
6 DZFL
7 DIF2
8 PSN
9 ^DZFR
Rch
LPF
10 AOUTRP
11 AOUTRN
12 VSS1
10u 0.1u
+
13 VDDR
+
14 VREFHR
10u 0.1u
15 VREFLR
AK4390
Top
View
LRCK 30
SDATA 29
BICK 28
PDN 27
DVDD 26
0.1u
VSS4 25
+
10u
MCLK 24
AVDD 23
+
0.1u 10u
VSS3 22
AOUTLP 21
AOUTLN 20
VSS2 19
0.1u
VDDL 18
10u
+
VREFHL 17
+
0.1u 10u
VREFLL 16
Lch
LPF
Lch
Mute
DSP
Lch Out
Digital
Ground
Analog
Ground
Analog 5.0V
+
Electrolytic Capacitor
Ceramic Capacitor
Notes:
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator
etc.
- VSS1/2/3/4 must be connected to the same analog ground plane.
- When AOUT drives a capacitive load, some resistance should be added in series between AOUT and the
capacitive load.
- All input pins except pull-down/pull-up pins should not be allowed to float.
Figure 12. Typical Connection Diagram (AVDD=5V, DVDD=5V, Serial Control Mode)
MS1046-E-00
- 27 -
2009/01