AK4390 Datasheet, PDF (15/32 Pages) Asahi Kasei Microsystems – Ultra Low Latency 32-Bit ΔΣ DAC

[AK4390]
■ Audio Interface Format
Data is shifted in via the SDATA pin using the BICK and LRCK inputs. Eight data formats are supported, selected by the
DIF2-0 pins (Parallel control mode) or DIF2-0 bits (Serial control mode) as shown in Table 4. In all formats the serial data
is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20-bit and 16-bit
MSB justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
4
5
6
7
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
Input Format
BICK
0
16bit LSB justified ≥ 32fs
1
20bit LSB justified ≥ 48fs
0
24bit MSB justified ≥ 48fs
1 24bit I²S Compatible ≥ 48fs
0
24bit LSB justified ≥ 48fs
1
32bit LSB justified ≥ 64fs
0
32bit MSB justified ≥ 64fs
1 32bit I²S Compatible ≥ 64fs
Table 4. Audio Interface Format
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Figure 5
Figure 5
Figure 6
(default)
LRCK
BICK
(32fs)
SDATA
Mode 0
BICK
(64fs)
SDATA
Mode 0
01
10 11 12 13 14 15 0 1
15 14
01
6 5 4 3 2 1 0 15 14
14 15 16 17
31 0 1
Don’t care
15 14
0 Don’t care
15:MSB, 0:LSB
Lch Data
Figure 1. Mode 0 Timing
10 11 12 13 14 15 0 1
6 5 4 3 2 1 0 15 14
14 15 16 17
31 0 1
15 14
0
Rch Data
LRCK
BICK
(64fs)
SDATA
Mode 1
SDATA
Mode 4
01
8 9 10 11 12
31 0 1
8 9 10 11 12
Don’t care
19
0 Don’t care
19
19:MSB, 0:LSB
Don’t care 23 22 21 20 19
0 Don’t care 23 22 21 20 19
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1/4 Timing
31 0 1
0
0
MS1046-E-00
- 15 -
2009/01