AK4390 Datasheet, PDF (18/32 Pages) Asahi Kasei Microsystems – Ultra Low Latency 32-Bit ΔΣ DAC

[AK4390]
■ Zero Detection
The AK4390 has a channel-independent zero detect function. When the input data for each channel is continuously zero
for 8192 LRCK cycles, the DZF pin of each channel goes to “H”. The DZF pin of each channel immediately returns to
“L” if the input data of either channel is not zero after going to “H”. If the RSTN bit is “0”, the DZF pins for both channels
go to “H”. The DZF pins of both channels go to “L” 4 ~ 5/fs after the RSTN bit returns to “1”. If the DZFM bit is set to
“1”, the DZF pins of both channels go to “H” only when the input data for both channels are continuously zero for 8192
LRCK cycles. The zero detect function can be disabled by setting the DZFE bit. In this case, DZF pins of both channels
are always “L”. The DZFB bit can invert the polarity of the DZF pin.
■ Soft Mute Operation
The soft mute operation is performed in the digital domain. When the SMUTE pin changes to “H” or the SMUTE bit set
to “1”, the output signal is attenuated by −∞ during ATT_DATA × ATT transition time from the current ATT level. When
the SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation
gradually changes to the ATT level during ATT_DATA × ATT transition time. If the soft mute is cancelled before
attenuating −∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle.
The soft mute is effective for changing the signal source without stopping the signal transmission.
SM UTE pin or
SM UTE bit
(1)
ATT_Level
A tte n u a tio n
(1)
(3)
-∞
GD
GD
(2)
(2)
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) ATT_DATA × ATT transition time (Table 9). For this example, the time is 1020LRCK cycles (1020/fs)
at ATT_DATA=255 in Normal Speed Mode.
(2) Analog output corresponding to digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
(4) When the input data for each channel is continuously zero for 8192 LRCK cycles, the DZF pin for each channel
goes to “H”. The DZF pin immediately returns to “L” if the input data are not zero after going “H”.
Figure 7. Soft Mute Function
■ System Reset
The AK4390 should be reset once by bringing the PDN pin = “L” upon power-up. The analog section exits power-down
mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during
4/fs.
MS1046-E-00
- 18 -
2009/01