AK4390 Datasheet, PDF (21/32 Pages) Asahi Kasei Microsystems – Ultra Low Latency 32-Bit ΔΣ DAC

[AK4390]
(2) RESET by MCLK or LRCK stop
The AK4390 is automatically placed in reset state when MCLK or LRCK is stopped during normal operation and the
analog outputs are floating (Hi-Z). When MCLK and LRCK are input again, the AK4390 exits reset state and starts the
operation. Zero detect function is disable when MCLK or LRCK is stopped.
AVDD pin
DVDD pin
RSTB pin
(1)
In ternal
Stat e
Power-down
Normal O peration
Digital Circuit P ower-down
Normal Operation
D/A In
(Dig ital )
Power-down
D/A Out
(Analog)
Clock In
MCLK, BICK, LRCK
Hi-Z
(4)
GD (2)
(3)
(4)
(5)
(4)
(5)
MCLK, BICK, LRCK Stop
GD (2)
Ex terna l
MUTE
(6)
(6)
(6)
Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be held “L” for 150ns.
(2) The analog output corresponding to digital input has the group delay (GD).
(3) Digital data can be stopped. The click noise after MCLK and LRCK are input again can be reduced by inputting
the “0” data during this period.
(4) Click noise occurs in 3 ∼ 4LRCK cycles ether on a rising edge (↑) of the PDN signal or MCLK inputs. This noise
is output even if “0” data is input.
(5) Mute the analog output externally if click noise (4) influences system application. The timing example is shown in
this figure.
Figure 10. Reset Sequence Example 2
MS1046-E-00
- 21 -
2009/01