AND8020 Datasheet, PDF (9/18 Pages) Analog Devices – Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure

AND8020/D
SECTION 3. THEVENIN EQUIVALENT PARALLEL TERMINATION
RR
RR
Although the single resistor termination to V_TT conserves
power, it requires an additional supply voltage. An alternate
approach to using a V_TT power supply is to use a resistor
divider network as shown in Figure 12 to develop a
Thevenin voltage, V_TT, and provide a parallel impedance
matching AC termination, the Thevenin parallel
termination.
V_CC
Driver
T−Line Z₀
R1
Receiver
*
R2
V_EE
V_CC
Driver
R1
* T−Line Z₀
* T−Line Z₀
*
R1
Receiver
*
* or Twisted Pair ^R2
R2
ǒ Ǔ ^{* VTT + VCC * 2.0V}
+ VCC
R2
R1 ) R2
(eq. 13)
V_EE
The Thevenin equivalent of the two resistors needs to be
equal to the characteristic impedance of the signal
transmission line. Calculated values for resistors R1 and R2
may be obtained from the following relationships.
ǒ Ǔ R2 + Z0
VCC * VEE
VCC * VTT
(eq. 14)
Where:
ǒ Ǔ R1 + R2
VCC * VTT
VTT _* VEE
(eq. 15)
V_TT = V_CC − 2.0 V
Z₀ = Characteristic Impedance of the Signal
Transmission Line
For a typical V_CC = 5.0 V PECL scheme, where V_EE =
GND, V_TT = 3.0 V, and Z₀ = 50 W:
ǒ Ǔ _{R2 + 50}
5*0
5*3
+ 125 W
(eq. 16)
ǒ Ǔ _{R1 + 125}
5*3
3*0
+ 83.3 W
(eq. 17)
and cross−checking for V_TT:
ǒ Ǔ _{VTT + 5}
125
125 ) 83.3
+ 3.0 V
(eq. 18)
VTT + VCC * 2.0 V + 3.0 V
(eq. 19)
For the typical V_CC = 3.3 V LVPECL scheme, where
V_EE = GND, V_TT = 1.3 V, and Z₀ = 50 W:
ǒ Ǔ _{R2 + 50}
3.3 * 0
3.3 * 1.3
+ 82.5 W
(eq. 20)
ǒ Ǔ _{R1 + 82.5}
3.3 * 1.3
1.3 * 0
+ 126 W
(eq. 21)
and cross−checking for V_TT:
ǒ Ǔ _{VTT + 3.3}
82.5
126 ) 82.5
+ 1.3 V
(eq. 22)
VTT + VCC * 2.0 V + 1.3 V
(eq. 23)
Figure 12. Thevenin Equivalent Parallel Termination
Differential ECL outputs can be terminated as independent
complimentary single−ended lines. Both sides of a
differential pair must be terminated. Balanced, symmetrical
loading of each line must be preserved.
While a Thevenin Parallel technique dissipates more
termination power, it does not require the additional V_TT
supply. This additional power is consumed entirely in the
external resistor divider network and thus will not change
the current being sourced by the device, hence it does not
alter the IC reliability or lifetime. As with standard parallel
termination, variance of V_TT and V_CC supplies must be
considered.
Table D. Thevenin Term Table
|V_CC−V_EE| = 5.0 V
Z₀ R1 R2
50 83 125
70 117 175
75 125 188
80 133 200
90 150 225
100 167 250
120 200 300
150 250 375
|V_CC−V_EE| = 3.3 V
Z₀ R1 R2
50 127 83
70 178 115
75 190 123
80 203 132
90 229 149
100 253 165
120 305 198
150 381 248
|V_CC−V_EE| = 2.5 V
Z₀ R1 R2
50 250 62.5
70 350 87.5
75 375 93.8
80 400 100
90 450 112.5
100 500 125.5
120 600 150
150 750 187.5
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