AND8020 Datasheet, PDF (13/18 Pages) Analog Devices – Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure

AND8020/D
For the 10E series (ECL mode operation),
where: V_OH = −0.9 V, V_SWING = 0.85 V, V_EE = −5.2 V:
(* 0.9) * (* 5.2)
Rt ) Rs ) Z0
y
0.531
Z0
(eq. 38)
7.10 * Z0 * Rs y Rt
For the 100E series (ECL mode operation),
where: V_OH = −0.955 V, V_SWING = 0.75 V, V_EE = −4.5 V:
(* 0.955) * (* 4.5)
Rt ) Rs ) Z0
y
0.468
Z0
6.57 * Z0 * Rs y Rt
(eq. 39)
Parallel Fanout of Series Termination
An extension of the series termination technique, using
parallel fanout, eliminates the problem of lumped loading at
the expense of extra transmission lines (Figure 17).
R_Sn
N number of lines
Driver
R_S1
Receiver n
*T−Line Z₀
*T−Line Z₀
R_t
V_EE
Receiver 1
Figure 17. Parallel Fanout Using Series Termination
Figure 17 shows a modification of the series termination
scheme in which several series terminated lines in parallel
fanout are driven using a single ECL gate. The principle
concern when applying this technique is to maintain the
current in the output emitter follower below the maximum
rated value. The value for R_t can be calculated by viewing
the circuit in terms of conductances.
Goutput u G1 ) G2n) G
(eq. 40)
From Table B, for each of the series:
(
1
Rt
)
y
1
( KZ₀ * Z01 * RS1)
)
(
KZ₀
*
1
Z02
*
RS2)
)
(
KZ₀
*
1
Z0n
* RS)
(eq. 41)
Where:
n = Number of Parallel Circuits
When:
Z01 + Z02 + Z0 _n, and RS1 + RS2 + RS _n (eq. 42)
Then R_t is calculated as:
Rt
x
(KZ0
*
n
Z0
r
*
Rs)
(eq. 43)
When a single series terminated line is driving more than
a single receiver, the maximum number of loads must be
addressed. The factor limiting the number of loads is the DC
voltage drop across the series termination resistor caused by
the summary input currents I_T during the receivers quiescent
high state. Noise margin loss, NM_loss, will probably
determine the acceptable DC voltage drop limit across R_s.
NMloss + IT * ( Rs + RO )
(eq. 44)
Where:
I_T = Sum of IINH Currents
R_O = Output Impedance of the Driver Gate
R_S = Termination Resistance
Driver
R_O
R_S
R_t
I_T ^{Receiver 1}
*T−Line Z₀
Receiver 2
V_EE
Receiver N
Figure 18. Noise Margin Loss Example
For the majority of ECL devices typical maximum value
for quiescent high state input current is 150 uA. Thus, for the
circuit shown in Figure 18, in which three gate loads are
present in a 50 W environment, the loss in high state noise
margin is calculated as:
NMloss + 3 * * 150 mA * 50 W + * 22.5 mV ^{(eq. 45)}
This represents a potential shift in the V_OH level of
−22.5 mV.
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