AND8020 Datasheet, PDF (15/18 Pages) Analog Devices – Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure

AND8020/D
SECTION 6. CAPACITIVE COUPLING
R
R
V_BB
R
R
R
V_CC
Although not strictly a termination, AC or capacitive
coupling is often used to provide features in conjunction
with proper termination. Such capabilities as hot swapping
capability, DC isolation to a receiver, and level shifting are
possible with capacitive coupling.
Data stream characteristics may impose restriction on
both termination and capacitive coupling. AC coupled
signals have the line DC blocked and will require a DC
restoration voltage, V_BIAS, for the receiver input. Data in
unencoded Non−Return−to−Zero (NRZ) format will require
DC restoration prior to AC coupling into a ECL receiver
input.
A sinusoidal waveform clock signal may be cap coupled
for conversion to a square wave with 50% duty cycle and
sharp rise and fall edges.
The capacitor used to couple the signal must have a
impedance rating of < 50 W over the frequency range of the
input signal. Because large capacitors appear somewhat
inductive at high frequencies, it may be necessary to use a
small capacitor in parallel with a larger one to achieve
satisfactory operation.
A coupling capacitor and the signal load impedance form
an RC network which will boundary the duration of a pulse.
Values for the R (load and leakage total resistance) and C
(coupling capacitor) should be selected to provide a time
constant, T_C, of at least 10x the pulse width. Data streams
may require larger T_C values to retain logic levels.
Hot Swapping
The desire often arises to remove or install a receiver or
daughter card without powering down the driver or
motherboard. This is termed “Hot Swapping”.
Powered Driver and an Unpowered Receiver
Damage Risk
Hot swapping presents a potential risk to an unpowered or
powered down ECL device receiver and driver in either the
Negative or Positive mode when driven by a typical signal
level.
When a receiver PECL receiver V_CC is off or powered
down, the V_CC Power Supply typically appears as a low
impedance source at 0.0 V capable of sinking considerable
current. Typical driver signal levels present voltages that
forward bias the input ESD protection diode structure and
the input base collector junction. Potentially lethal current
paths may develop through forwarded junctions to V_CC.
There is also a risk for a powered down or off NECL or
LVNECL receiver and driver. A V_EE supply will typically
appear as a low impedance path to 0.0 V (GND). Typical
negative levels present signal voltages that will forward bias
the input ESD protection diode structure and the input base
collector junction to this low impedance path. Potentially
lethal current paths may develop through the forwarded
junctions and V_EE to 0.0 V.
Powered down receiver risk may be managed in several
ways.
1. Physical Sequencing − the supplies for V_EE
(Ground) and V_CC (Power) may be physically
connected prior to signal lines by altering the
daughter board edge connection geometry, making
V_EE and V_CC connectors protrude and engage or
sequence first. V_EE connectors could even be
sequenced prior to V_CC. This insures the supplies
are powered prior to input signal voltages.
2. Switching − a relay (or analog switch) could be
used to open or close the supply lines insuring the
power supply line is opened when powered off.
3. Cap Coupling − DC isolation of potentially
damaging current.
4. Series R − an additional series impedance matching
resistor, R_S, will act as power splitter with an
existing parallel termination resistor, R_T, to
accomplish some current limiting to help manage
the risk. This will also attenuate the amplitude
50%, easily tolerated by most high gain, high input
sensitivity devices.
Using V_BB Pin for V_BIAS
Some devices provide a convenient V_BB pin for use as a
VBIAS reference supply to rebias a DC level. A DC rebias
level must be at the common mode voltage of the input
signal to properly preserve a 50% output duty cycle (see
AND8066). A package V_BB pin may provide an internally
generated DC switching reference voltage for the device
inputs, and is available only to the package input pins. Do not
port one package V_BB pin directly to another device without
current amplification. When used, decouple V_BB to V_CC (or
V_TT) via a 0.01 to 0.001 mF capacitor to suppress noise
injection. Limit current to less than 0.5 mA (Absolute
Maximum Rating source or sink) as shown in Figure 21.
When not used, V_BB should be left open.
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