AND8020 Datasheet, PDF (2/18 Pages) Analog Devices – Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure

AND8020/D
INTRODUCTION
Static DC Termination Analysis
A standard Emitter Coupled Logic (ECL) output driver
typically uses a current switching differential with an emitter
follower for level shifting the output and the internal CML
levels to familiar ECL levels. This output driver architecture
presents about 6−8 W internal impedance in both LOW and
HIGH states when properly current biased. This results in a
typical V_PP signal of 800 mV_PP (measured single−endedly on
each line) swinging around a DC voltage point of
V_CC − 1.3 V when properly terminated and operating
correctly as shown in Figure 1.
V_CC
V_CC
8 W Internal Output
Impedance
Q
D
V_EE
Driver
Q
R_E
D
R_E
V_EE
V_EE
Receiver
Figure 1. Typical ECL Output with Emitter Follower Output Structure,
Typical Termination, and Typical ECL Input Interconnect
For proper static and dynamic operation, the output
emitter follower transistor must remain in the active region
of operation which requires an external resistive path be
provided from the output pin to a voltage more negative than
worst case V_OL, such as V_EE. The resistor, R_E, is considered
a current bias for the Emitter Follower output structure.
When properly terminated and current biased (loaded),
the outputs will generate both: (1) static state voltage levels
V_OL (LOW) or V_OH (HIGH) and (2) a dynamic transition
edge (tr or tf) between state levels.
Static State Voltage Levels
Figure 2 illustrates the typical relationship of static signal
levels and dynamic transition edges between an Output
Driver Signal and a Receiver Input Signal. Both outputs of
a differential driver should always be terminated and loaded
as identically as possible to preserve minimum skew and
jitter operation of the device.
Output
Driver
Signal _VCC
V_OH
V_OL
Input
Receiver
Signal
V_IH
V_CC −1.3 V
V_IL
V_EE
tr
tf
V_CC
V_OH
V_OL
V_IH
V_CC −1.3 V
V_IL
V_EE
tf
tr
Figure 2. State Levels V_OH, V_OL,
and Dynamic Transitions at Q or Q and D or D
http://onsemi.com
2