AND8020 Datasheet, PDF (16/18 Pages) Analog Devices – Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure

AND8020/D
A. Differential
V_CC
* 0.001 mF
IN
INb
0.001 mF
1 kW
Rpu 25 kW to 100 kW
Receiver
OUT
OUT
V_BB R_t
R_t
0.01 − 0.001 mF
V_TT
V_CC or V_TT
B. Single−Ended
V_CC
* 0.001 mF
IN
1 kW
Rpu 25 kW to 100 kW
Receiver
OUT
OUT
V_{BB Rt}
R_t
0.01 − 0.001 mF
V_TT
V_CC or V_TT
* High Voltage Cap May Be Needed
Figure 21. Differential and Single−Ended AC
Configurations Using V_BB Reference
In Figure 21A, the IN line has a 1 kW resistor to V_BB,
presenting a 1 KW impedance across the differential signal
lines. This assumes the signal impedance matching has been
accomplished prior to the cap coupling, on the driver side of
cap. Locate the coupling capacitor as physically close to the
input pin as possible to minimize the trace length and
diminish potential reflections due to the impedance
mismatch.
If signal impedance matching has not been accomplished
prior to the cap coupling, then a characteristic impedance
resistor, 2Z₀, would be used across the input lines, on the
receiver side of the cap. The value of the Rpu resistor would
be adjusted to produce an acceptable null signal default
voltage drop.
Auto−Oscillation Suppression with V_BB
If the differential inputs to the AC coupled device are left
open or if the driving signals are lost, both receiver input pin
voltages converge toward the VBIAS reference voltage V_BB
value. Sustained oscillation may autonomously result from
a combination of ambient environmental noise, the device
small signal gain, and feedback from the output to the input
through parasitic capacitive and inductive paths.
As a differential receiver input voltage diverges, the
output responds by transitioning toward a state voltage. A
sufficient voltage D across the receiver inputs will force the
output to state level. Depending on conditions, about 10 to
50 mV is sufficient to suppress instability oscillation and
force a determined state on the output.
For the configuration using the V_BB reference, Figure 21,
this input voltage D may be accomplished by injecting a
minimum current from V_CC through an external pullup
resistor, Rpu, on ONE input line. The value of Rpu could
range from 25 kW to 100 kW. As Rpu increases, the phase
error is diminished and the susceptibility to oscillation
increases.
Generally, an internal pull−down resistor ranging in value
from 52 kW to 75 kW is deployed on an input pin. On some
D−bar (Invert) input pins an additional 36 kW to 75 kW
resistor is deployed to suppress oscillation by forcing a
determined state on the output under open input or null
voltage conditions. A minimum input voltage D of 20 to
30 mV may be effective depending on noise, gain, and
layout.
Generating V_BB for VBIAS
When V_BB voltages are desired, but not available within
a device, the reference level may be ported from a generator
as illustrated in Figure 22. Any of the “16” type buffers are
recommended for use in a high current gain V_BB Generator
buffer. For example, the E416, EL16, LVEL16, EP16,
LVEP16, EL17, LVEL17, etc. type devices have a V_BB pin
available for constructing a V_BB Generator buffer.
1 KW
16
V_BB
V_BB(out)
RT
0.01 mF
V_TT
V_CC or V_TT
Figure 22. V_BB Voltage Reference Generator
Non−V_BB Biasing
Alternative to a device supplied V_BB, any voltage source
may be supplied to bias receiver inputs to provide an
acceptable V_IHCMR (Voltage Input HIGH Common Mode
Range) DC reference to the receiver (see specific device data
sheet). Signal impedance matching may be accomplished
prior to cap coupling, allowing a wide range values for a
rebiasing resistor network.
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