AND8020 Datasheet, PDF (10/18 Pages) Analog Devices – Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure

AND8020/D
Because the resistor divider network of R1 and R2 is used
to generate V_TT, the variation in V_TT will be intimately tied
to the variation in V_CC. Differentiating the equation for V_TT
with respect to V_CC yields:
DVTT
DVCC
+
(
R2
R1 ) R2 )
DVCC
(eq. 24)
For the nominal case, this equation reduces to:
DVTT + 0.6 DVCC
(eq. 25)
If DV_CC = $5% = $0.25 V, then DV_TT = $0.15 V.
As mentioned previously, the real potential for problems
will be if the V_OL level can potentially put the output emitter
follower out of the active operating region and into cutoff.
Because of the relationship between the V_CC and V_TT levels,
the only cutoff risk condition occurs at V_CCmin, the lowest
value of V_CC. Applying the equation for I_OLmin under this
−5% V_CC condition yields:
IOLmin
+
(
VOLmin *
Rt
VTT
)
(eq. 26)
IOLmin
+
(4.75
*
1.85)
50
*
2.85
+
1.0
mA
(eq. 27)
The results of this cutoff risk analysis show there is no
potential for the output emitter follower to be in cutoff. This
would indicate a Thevenin equivalent termination scheme is
more robust to variation in V_CC. Since the designer has the
flexibility of choosing the V_TT level via the selection of the
R1 and R2 resistors, the following procedure can be used.
At −5% minimal variation case for V_CC:
V_CC = 4.75 V
V_TT = V_CC − 2.0 V = 2.75 V
R2 = 119 W
R1 = 86 W
Thus:
I_OHmax = 23 mA
I_OLmin = 3.0 mA
At +5% minimal variation case for V_CC:
V_CC = 5.25 V
V_TT = 3.05 V
Thus:
I_OHmax = 28 mA
I_OLmin = 5.2 mA
Although the output currents are slightly higher than
nominal, the elimination of emitter follower cutoff risk is
well justified.
When the equivalent termination resistance matches the
line impedance, no reflection occurs because all the energy
in the signal is dissipated by the termination. Hence, in
comparing properly terminated schemes parallel and
Thevenin, a primary consideration is the power supply
requirements. As mentioned earlier, the parallel V_TT scheme
requires an extra power supply; however, the Thevenin
termination dissipates 10 times more DC power.
Fortunately, this extra power dissipation cannot be seen on
the die; therefore, either technique results in similar die
junction temperatures.
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