AND8020 Datasheet, PDF (17/18 Pages) Analog Devices – Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure

AND8020/D
When the coupling capacitor is physically located near
enough to the receiver input pins to prohibit reflections on the
connecting trace length or signal impedance matching has
been accomplished prior to cap coupling, then a simple high
value resistor divider network from V_CC to V_EE is
recommended as shown in Figure 23. Differential and
Single−Ended AC Configurations Using Non−V_BB Biasing
(A and B). This network total resistance may be from 1 KW
to 10 KW. For 50 W impedance traces, the typical value for the
voltage divider resistors are given in Table F. Typical Rebias
and Impedance Matching Resistor Network Values @
Z₀ = 50. Note the impedance presented to a signal is u5 KW.
Table F. Typical Rebias and Impedance Matching Resistor Network Values @ Z₀ = 50
Resistor
R1 (R1′)
|V_CC−V_EE| = 5.0 V
4
|V_CC−V_EE| = 3.3 V
4
|V_CC−V_EE| = 2.5 V
4
R2 (R2′)
6
6
6
V_rebias
3.3
2.2
1.7
Units
KW
KW
V
When the coupling capacitor is physically located at a
distance from receiver over a trace or cable length capable
of sustaining reflections, a Thevenin parallel network
matching the line of impedance is recommended for their
suppression. This is shown in Figure 23. Differential and
Single−Ended AC Configurations Using Non−V_BB Biasing
(A and B). The rebias voltage may always be safely set at
V_CC−1.3. For 50 W impedance traces, the typical value for
the voltage divider resistors are given in Table G. Typical
Rebias and Impedance Matching Resistor Network Values @
Z₀ = 50.
Table G. Typical Rebias and Impedance Matching Resistor Network Values @ Z₀ = 50
Resistor
|V_CC−V_EE| = 5.0 V
|V_CC−V_EE| = 3.3 V
|V_CC−V_EE| = 2.5 V
R1 (R1′)
68
83
96.15
R2 (R2′)
192
127
104.16
V_rebias
3.7
2.0
1.2
Units
W
W
V
A. Differential
V_CC
R1
0.001 mF
IN
INb
0.001 mF
R2
R1Ȁ
Receiver
R2Ȁ
R_t
OUT
OUTb
R_t
V_EE
V_TT
B. Single−Ended
V_CC
R1
0.001 mF
IN
R1Ȁ
Receiver
OUT
OUTb
R2
R2Ȁ
R_t
R_t
V_EE
V_TT
Figure 23. Differential and Single−Ended AC
Configurations Using Non−V_BB Biasing
The characterized V_BB reference voltage bias, VBIAS, is
V_CC − 1.33 V, but a device is not restricted to this VBIAS
value. The VBIAS range is determined by the Vpp
amplitude and the signal HIGH level, V_IH. Input HIGH
level, V_IH, is constrained by the data sheet specification of
common mode range, V_IHCMR or V_CMR. Thus, the VBIAS
range is constrained:
VBIAS _max + VIHCMRmax * ( 0.5 ) ( Vpp )
VBIAS _min + VIHCMRmin * ( 0.5 ) ( Vpp )
A single−ended source into a differential type input signal
amplitude swing, V_pp, is typically constrained from
V_ppmin = 300 mV to V_ppmax = 1000 mV.
An input signal must swing symmetrically above and
below VBIAS to preserve a 50% duty cycle out of the
receiver. Differential signals must have identical crosspoint
voltages to preserve minimum phase error and duty cycle
error. Crosspoint voltages are determined by the matched
precision of the resistor divider network from V_CC to V_EE.
Auto−Oscillation Suppression without V_BB
For a configuration without a V_BB reference pin, such as
illustrated in Figure 23, the resistor network may be
modified to have an input voltage D of 20 to 30 mV offset
between the input pins. Either a high resistor value divider
or a Thevenin parallel network may be modified to
accomplish this input voltage D. This is accomplished by
altering the values of R1, R1′, R2, and R2′.
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