AND8020 Datasheet, PDF (8/18 Pages) Analog Devices – Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure

AND8020/D
Internal 100 W Termination (LVDS)
For some technologies, such as LVDS, this passive 100 W
internal termination can provide sufficient termination for the
driver as shown in Figure 10. Devices with a Combo Pin will
require this pin to remain open, while devices with singulated
internal resistors require the two pinned out V_t nodes for a
differential pair to be shorted together to provide the 100 W
termination.
LVDS Driver
*T−Line Z₀
*T−Line Z₀
(*or twisted pair)
Open V_t Pin
Receiver
RR
Internal Termination Combo Pin
LVDS Driver
*T−Line Z₀
*T−Line Z₀
(*or twisted pair)
Vt1
Shorted
Vt2
Receiver
RR
Internal Termination Singulated Pins
Figure 10. LVDS Interconnect with Internal
Termination
Differential ECL outputs can be terminated as independent
complimentary single−ended lines. Both sides of any
differential pair must be terminated as identically as possible
to minimize phase error and pulse width duty cycle skew.
The I_OH currents in these two cases will vary the DC V_OH
levels by $40 mV. However in the vast majority of cases, DC
levels are well centered in their specification windows, thus
this variation will simply move the level within the valid
specification window and no loss of worst case noise margin
will be seen.
The I_OL situation on the other hand does pose a potential
AC problem. In the worst Case #1 I_OLmin situation, the
output emitter follower could move into the cutoff state
(0 mA). The output emitter followers of ECL devices are
designed to be in the conducting, active region of operation
at all times. When forced into cutoff, the delay of the device
will be increased due to the extra time required to pull the
output emitter follower out of the cutoff state. Again, this
situation will arise only under a number of simultaneous
worst case situations and therefore, is highly unlikely to
occur. But, because of the potential, it should not be
overlooked.
Output Drive Characteristics
Figure 11 shows the nominal output characteristics for
ECL devices operating in negative ECL mode, driving
various load impedances (including the standard 50 W)
returned to a negative two volt supply. The output
resistances, RH (high state output resistance) and RL (low
state output resistance), are obtained from the reciprocal of
the slope at the desired operating point. Many applications
require loads other than 50 W − the resulting V_OH and V_OL
levels can be estimated using the following technique.
0
SLOPE = 6 W − 8 W
−5
150 W
−10
to − 2.0 V
−15
−20
−25
V_OL
−30
−35
−40
−2.0 −1.75
25 W
to − 2.0 V
−1.5 −1.25
V_OH
100 W
to − 2.0 V
50 W
to − 2.0 V
T_A =25°C
−1.0 −0.75 −0.5 −0.25 0
OUTPUT VOLTAGE (V)
Figure 11. Normal Output Levels Driving Various
Load Impedances
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