AND8020 Datasheet, PDF (1/18 Pages) Analog Devices – Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure

AND8020/D
Termination of ECL
Logic Devices with
EF (Emitter Follower)
OUTPUT Structure
Prepared by: Paul Shockman
ON Semiconductor Logic Applications Engineering
http://onsemi.com
APPLICATION NOTE
CONTENTS OF APPLICATION NOTE
Introduction − DC Termination Analysis
Section 1. Unterminated Lines
R_E
V_EE
Section 2. Parallel Termination − External and Internal
External
R_t
R_E R_E
V_EE
Near (Standard Pair)
Internal
R_t
R_t
V_TT
Far (Standard Pair)
R_E R_E
V_{EE Vto}
R_t ^Rt
(Open)
Vt
R_t ^Rt
V_TT
Section 3. Thevenin Equivalent/Parallel Termination
RR
RR
Section 4. Series (Back) Termination
R
R
R_E
R_E
Section 5. Diode Termination
V_BB
Driver
D1
*
*
D2
Receiver
*All Media ^D1
D2
V_BB
Section 6. Capacitive Coupling
R_E R_{E Vt1}
V_EE ^Vt2
R_t R_t
(Shorted)
Near (Standard Pair)
Vt1
R_t R_t
Vt2
V_TT
Far (Standard Pair)
© Semiconductor Components Industries, LLC, 2004
1
July, 2004 − Rev. 5
R
V_BB
R R RR
V_CC
Publication Order Number:
AND8020/D