AND8020 Datasheet, PDF (5/18 Pages) Analog Devices – Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure

AND8020/D
TERMINATION OF ECL LOGIC DEVICES
SECTION 2. PARALLEL TERMINATION − EXTERNAL AND INTERNAL
External
Internal
R_t
R_E
R_E
V_EE
Near (Standard Pair)
R_E R_E
V_{EE Vto}
R_t ^Rt
(Open)
Vt
R_t ^Rt
V_TT
R_t
R_t
V_TT
Far (Standard Pair)
R_E R_{E Vt1}
R_t R_t
V_EE ^Vt2
(Shorted)
Near (Standard Pair)
Vt1
R_t R_t
Vt2
V_TT
Far (Standard Pair)
Parallel termination advantages:
• Method of choice for best circuit performance
• Particularly excellent for driving distributed loads
• Undistorted waveform along the full length of the line
• Decreased power consumption.
Far DC Current Return − V_TT
A parallel terminated line is one in which the receiving end
is signal terminated internally or externally (usually to a
voltage V_TT) through a resistor (R_t) with a value equal to the
line characteristic impedance (Figure 4). This line also carries
the biasing current for the drivers output far from the driver.
Output current and power dissipation is decreased due to use
of a V_TT termination supply. The V_TT supply must sustain the
emitter follower output transistor in its active operating region
under all operating conditions. A minimum continuous current
occurs for the most negative V_OL, therefore the V_TT supply
must remain more negative than the worst case V_OLmin and
always sink current.
Standard V_TT is 2.0 V below V_CC supply. A parallel
resistor, R_t, matching the controlled impedance transmission
line, Z₀, connects the signal to the V_TT supply. The Parallel
Termination to V_TT is shown in Figure 4. The termination
resistors may be internal or external and either ganged into a
Combo pin or offered as Singulated pins. Some devices may
have each internal resistors independently pinned out,
allowing further termination versatility.
Driver
*T−Line Z₀
*T−Line Z₀
(*or twisted pair)
Receiver
R_t
R_t
V_TT
External (Far, Diff.)
Driver
*T−Line Z₀
*T−Line Z₀
(*or twisted pair)
Receiver
RR
V_TT Vt
Internal Termination Combo Pin (Far, Diff.)
Driver
T−Line Z₀
R_t = Z₀
V_TT = V_CC −2.0 V
R_t
V_TT
Receiver
Driver
*T−Line Z₀
*T−Line Z₀
(*or twisted pair)
Vt1
V_{TT Vt2}
Receiver
RR
External (Far, S.E.)
Internal Termination Singulated Pins (Far, Diff.)
Figure 4. Parallel Termination to V_TT − Differential and Single−Ended with Combo or Singulated Vt Pins (Far Return)
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