AND8020 Datasheet, PDF (6/18 Pages) Analog Devices – Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure

AND8020/D
Internal Termination Resistors
Internal termination conveniently uses 50 W values for R_t,
with the most popular being Z₀. Note the internal termination
allows the Combo Pin node, V_t, from the internal resistors to
be connected to an external V_TT supply, typically at
V_CC − 2.0 V, as shown in Figure 5. Alternatively, this Combo
Pin may be pulled to V_EE through an external resistor to form
a “Y” type termination variant, as shown in Figure 5. See the
“Y Variance” topic and the “Y Term Table” for R_t3 resistor
values.
Driver
A.
*T−Line Z₀
*T−Line Z₀
(*or twisted pair)
Receiver
RR
V_TT Connection
V_TT
Driver
B.
*T−Line Z₀
*T−Line Z₀
(*or twisted pair)
Receiver
RR
Y Connection
R_t3
V_EE
Figure 5. Combo Pin V_TT or “Y” Connection with
Internal Parallel Termination
Example Calculations
Ideally, V_TT supply tracks 1:1 with V_CC; however, supply
tolerances need to be considered. Assume for instance a
MC10EP16, +85°C, nominal +3.3 V_CC, terminated 50 W (R_t)
to V_TT, where V_TT is V_CC − 2.0 V, or 1.3 V:
IOHmax of (VCC ) * 0.885 V
IOLmin of (VCC ) * 1.685 V
resulting in the nominal case:
IOHmax
+
(VOHmax *
Rt
VTT
)
(3.3
*
0.885)
50
*
1.3
+
22.3
mA
IOLmin
+
(VOLmin *
Rt
VTT
)
(3.3
*
1.685)
50
*
1.3
+
6.3
mA
If +5% tolerances are assumed, two worst case conditions result.
Case #1: V_CCmin = V_CC − 5%, V_TTmax = V_TT + 5%
IOHmax
+
(VOHmax
Rt
*
VTT)
((3.135
*
0.885)
50
*
1.365)
+
17.7
mA
IOLmin
+
(VOLmin *
Rt
VTT)
((3.135
*
1.685)
50
*
1.365)
+
1.7
mA
Case #2: V_CCmin + 5%, V_TTmax − 5%
IOHmax
+
(VOHmax
Rt
*
VTT)
((3.465
*
0.885)
50
*
1.235)
+
26.9
mA
IOLmin
+
(VOLmin *
Rt
VTT)
((3.465
*
1.685)
50
*
1.235)
+
1.09
mA
Y Variance
The “Y” termination for a differential pair may be
preferred when avoiding the use of a V_TT supply. The design
is shown in Figure 6 and utilizes the following formulas for
calculating resistor values which are found in the Y Term
Table. The voltage at the Node where R_t1, R_t2, and R_t3
connect remains at a static V_TT voltage of V_CC − 2.0 V, or
1.3 V.
Rt1 + Rt2 + Z0
(eq. 10)
ǒ Ǔ Rt3 + Rt1
VTT _* VEE
VOH ) VOL * 2VTT
(eq. 11)
VTT
+
Rt3
(
VOH
) VOL
Rt1 )
))(
2Rt3
Rt1
*
VEE )
(eq. 12)
Driver
*T−Line Z₀
*T−Line Z₀
* or Twisted Pair _Rt1
Receiver
R_t2
R_t3
C₁ 0.1−0.01 mF
V_CC
Figure 6. “Y” Variance
http://onsemi.com
6