PROASIC3E Datasheet, PDF (8/37 Pages) Actel Corporation – I/O Structures in IGLOOe and ProASIC3E Devices

I/O Structures in IGLOOe and ProASIC3E Devices
I/O Architecture
I/O Tile
The I/O tile provides a flexible, programmable structure for implementing a large number of I/O
standards. In addition, the registers available in the I/O tile can be used to support high-
performance register inputs and outputs, with register enable if desired (Figure 3). The registers
can also be used to support the JESD-79C Double Data Rate (DDR) standard within the I/O structure
(see DDR for Actel’s Low-Power Flash Devices for more information).
As depicted in Figure 3, all I/O registers share one CLR port. The output register and output enable
register share one CLK port.
To FPGA Core
I/O / Q0
1
Input
Register
CLR/PRE
I/O / Q1
3
Input
ICE ^Register
CLR/PRE
I/O / ICLK
2
Input
Register
Y _{Pull-Up/-Down}
Resistor Control
PAD
Signal Drive Strength
and Slew Rate Control
A
E = Enable Pin
From FPGA Core
I/O / D0
I/O / D1 / ICE
I/O / OCLK
I/O / OE
I/O / CLR or I/O / PRE / OCE
Figure 3 • I/O Block Logical Representation
4
Output
OCE _Register
CLR/PRE
5
ICE Output
Register
CLR/PRE
6
OCE
Output
Enable
Register
CLR/PRE
8
v1.4