PROASIC3E Datasheet, PDF (10/37 Pages) Actel Corporation – I/O Structures in IGLOOe and ProASIC3E Devices

I/O Structures in IGLOOe and ProASIC3E Devices
Output Buffer
Hot-Swap, 5 V Tolerance, and
Clamp Diode Control
V_CCI
V_CCI V_CCI
OE
(from core logic)
Output Buffer
Logic and
Enable Skew
Circuit
Drive
Strength
and
Output
Slew Rate
Control
Output Signal
(from core logic)
Weak
Pull-Up
Control
(from
core)
ESD Protection¹
Clamp Diode
I/O PAD
Clamp Diode
Weak
Pull-
Down
Control
(from
core)
ESD Protection¹
Input Buffer
Input Buffer Standard²
and Schmitt Trigger
Control
Input Signal to Core Logic _{Programmable Input}
Delay Control
Notes:
1. All NMOS transistors connected to the I/O pad serve as ESD protection.
2. See Table 2 on page 3 for available I/O standards.
Figure 5 • Simplified I/O Buffer Circuitry
I/O Registers
Each I/O module contains several input, output, and enable registers. Refer to Figure 5 for a
simplified representation of the I/O block. The number of input registers is selected by a set of
switches (not shown in Figure 3 on page 8) between registers to implement single-ended or
differential data transmission to and from the FPGA core. The Designer software sets these
switches for the user. A common CLR/PRE signal is employed by all I/O registers when I/O register
combining is used. Input Register 2 does not have a CLR/PRE pin, as this register is used for DDR
implementation. The I/O register combining must satisfy certain rules.
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