PROASIC3E Datasheet, PDF (1/37 Pages) Actel Corporation – I/O Structures in IGLOOe and ProASIC3E Devices

I/O Structures in IGLOOe and ProASIC3E Devices
Introduction
Low-power flash devices feature a flexible I/O structure, supporting a range of mixed voltages (1.2 V,
1.5 V, 1.8 V, 2.5 V, and 3.3 V) through bank-selectable voltages. IGLOO^®e, ProASIC^®3EL, and
ProASIC3E families support Pro I/Os.
Users designing I/O solutions are faced with a number of implementation decisions and
configuration choices that can directly impact the efficiency and effectiveness of their final design.
The flexible I/O structure, supporting a wide variety of voltages and I/O standards, enables users to
meet the growing challenges of their many diverse applications. The Actel Libero^® Integrated
Design Environment (IDE) provides an easy way to implement I/O that will result in robust I/O
design.
This document first describes the two different I/O types in terms of the standards and features
they support. It then explains the individual features and how to implement them in Actel's Libero
IDE.
To FPGA Core
I/O / Q0
1
Input
Register
CLR/PRE
I/O / Q1
3
Input
ICE ^Register
CLR/PRE
I/O / ICLK
2
Input
Register
Y _{Pull-Up/-Down}
Resistor Control
Scan
PAD
Scan
Signal Drive Strength
Scan and Slew Rate Control
A
E = Enable Pin
From FPGA Core
I/O / D0
I/O / D1 / ICE
I/O / OCLK
I/O / OE
I/O / CLR or I/O / PRE / OCE
4
Output
OCE _Register
CLR/PRE
5
ICE Output
Register
CLR/PRE
6
OCE
Output
Enable
Register
CLR/PRE
Figure 1 • I/O Block Logical Representation
v1.4
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