PROASIC3E Datasheet, PDF (27/37 Pages) Actel Corporation – I/O Structures in IGLOOe and ProASIC3E Devices

I/O Structures in IGLOOe and Pro ASIC3E Devices
I/O Register Combining
Every I/O has several embedded registers in the I/O tile that are close to the I/O pads. Rather than
using the internal register from the core, the user has the option of using these registers for faster
clock-to-out timing, and external hold and setup. When combining these registers at the I/O buffer,
some architectural rules must be met. Provided these rules are met, the user can enable register
combining globally during Compile (as shown in the "Compiling the Design" section in the I/O
Software Control in Low-Power Flash Devices section of the handbook).
This feature is supported by all I/O standards.
Rules for Registered I/O Function:
1. The fanout between an I/O pin (D, Y, or E) and a register must be equal to one for combining
to be considered on that pin.
2. All registers (Input, Output, and Output Enable) connected to an I/O must share the same
clear or preset function:
– If one of the registers has a CLR pin, all the other registers that are candidates for
combining in the I/O must have a CLR pin.
– If one of the registers has a PRE pin, all the other registers that are candidates for
combining in the I/O must have a PRE pin.
– If one of the registers has neither a CLR nor a PRE pin, all the other registers that are
candidates for combining must have neither a CLR nor a PRE pin.
– If the clear or preset pins are present, they must have the same polarity.
– If the clear or preset pins are present, they must be driven by the same signal (net).
3. Registers connected to an I/O on the Output and Output Enable pins must have the same
clock and enable function:
– Both the Output and Output Enable registers must have an E pin (clock enable), or none
at all.
– If the E pins are present, they must have the same polarity. The CLK pins must also have
the same polarity.
In some cases, the user may want registers to be combined with the input of a bibuf while
maintaining the output as-is. This can be achieved by using PDC commands as follows:
set_io <signal name> -REGISTER yes ------register will combine
set_preserve <signal name> ----register will not combine
Weak Pull-Up and Weak Pull-Down Resistors
When the I/O is pulled up, it is connected to the V_CCI of its corresponding I/O bank. When it is
pulled down, it is connected to GND. Refer to the datasheet for more information.
For low-power applications, configuration of the pull-up or pull-down of the I/O can be used to set
the I/O to a known state while the device is in Flash*Freeze mode. Refer to Flash*Freeze
Technology and Low-Power Modes in IGLOO and ProASIC3L Devices for more information.
The Flash*Freeze (FF) pin cannot be configured with a weak pull-down or pull-up I/O attribute, as
the signal needs to be driven at all times.
Output Slew Rate Control
The slew rate is the amount of time an input signal takes to get from logic LOW to logic HIGH or
vice versa.
It is commonly defined as the propagation delay between 10% and 90% of the signal's voltage
swing. Slew rate control is available for the output buffers of low-power flash devices. The output
buffer has a programmable slew rate for both HIGH-to-LOW and LOW-to-HIGH transitions. Slew
rate control is available for LVTTL, LVCMOS, and PCI-X I/O standards. The other I/O standards have a
preset slew value.
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