PROASIC3E Datasheet, PDF (18/37 Pages) Actel Corporation – I/O Structures in IGLOOe and ProASIC3E Devices

I/O Structures in IGLOOe and ProASIC3E Devices
IGLOOe and ProASIC3E
For devices requiring Level 3 and/or Level 4 compliance, the board drivers connected to the I/Os
must have 10 kΩ (or lower) output drive resistance at hot insertion, and 1 kΩ (or lower) output
drive resistance at hot removal. This resistance is the transmitter resistance sending a signal toward
the I/O, and no additional resistance is needed on the board. If that cannot be assured, three levels
of staging can be used to achieve Level 3 and/or Level 4 compliance. Cards with two levels of
staging should have the following sequence:
• Grounds
• Powers, I/Os, and other pins
Cold-Sparing Support
Cold-sparing refers to the ability of a device to leave system data undisturbed when the system is
powered up, while the component itself is powered down, or when power supplies are floating.
Cold-sparing is supported on ProASIC3E devices only when the user provides resistors from each
power supply to ground. The resistor value is calculated based on the decoupling capacitance on a
given power supply. The RC constant should be greater than 3 µs.
To remove resistor current during operation, it is suggested that the resistor be disconnected (e.g.,
with an NMOS switch) from the power supply after the supply has reached its final value. Refer to
the Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the ProASIC3 and ProASIC3E
handbooks for details on cold-sparing.
Cold-sparing means that a subsystem with no power applied (usually a circuit board) is electrically
connected to the system that is in operation. This means that all input buffers of the subsystem
must present very high input impedance with no power applied so as not to disturb the operating
portion of the system.
The 30 k gate devices fully support cold-sparing, since the I/O clamp diode is always off (see Table 13
on page 19). If the 30 k gate device is used in applications requiring cold-sparing, a discharge path
from the power supply to ground should be provided. This can be done with a discharge resistor or
a switched resistor. This is necessary because the 30 k gate devices do not have built-in I/O clamp
diodes.
For other IGLOOe and ProASIC3E devices, since the I/O clamp diode is always active, cold-sparing
can be accomplished either by employing a bus switch to isolate the device I/Os from the rest of the
system or by driving each I/O pin to 0 V. If the resistor is chosen, the resistor value must be
calculated based on decoupling capacitance on a given power supply on the board (this decoupling
capacitance is in parallel with the resistor). The RC time constant should ensure full discharge of
supplies before cold-sparing functionality is required. The resistor is necessary to ensure that the
power pins are discharged to ground every time there is an interruption of power to the device.
IGLOOe and ProASIC3E devices support cold-sparing for all I/O configurations. Standards, such as
PCI, that require I/O clamp diodes can also achieve cold-sparing compliance, since clamp diodes get
disconnected internally when the supplies are at 0 V.
When targeting low-power applications, I/O cold-sparing may add additional current if a pin is
configured with either a pull-up or pull-down resistor and driven in the opposite direction. A small
static current is induced on each I/O pin when the pin is driven to a voltage opposite to the weak
pull resistor. The current is equal to the voltage drop across the input pin divided by the pull
resistor. Refer to the "Detailed I/O DC Characteristics" section of the appropriate family datasheet
for the specific pull resistor value for the corresponding I/O standard.
For example, assuming an LVTTL 3.3 V input pin is configured with a weak pull-up resistor, a
current will flow through the pull-up resistor if the input pin is driven LOW. For LVTTL 3.3 V, the
pull-up resistor is ~45 kΩ, and the resulting current is equal to 3.3 V / 45 kΩ = 73 µA for the I/O pin.
This is true also when a weak pull-down is chosen and the input pin is driven HIGH. This current can
be avoided by driving the input LOW when a weak pull-down resistor is used and driving it HIGH
when a weak pull-up resistor is used.
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