PROASIC3E Datasheet, PDF (29/37 Pages) Actel Corporation – I/O Structures in IGLOOe and ProASIC3E Devices

I/O Structures in IGLOOe and Pro ASIC3E Devices
Simultaneously Switching Outputs (SSOs) and Printed Circuit
Board Layout
Each I/O voltage bank has a separate ground and power plane for input and output circuits
(VMV/GNDQ for input buffers and V_CCI/GND for output buffers). This isolation is necessary to
minimize simultaneous switching noise from the input and output (SSI and SSO). The switching
noise (ground bounce and power bounce) is generated by the output buffers and transferred into
input buffer circuits, and vice versa.
Since voltage bounce originates on the package inductance, the VMV and V_CCI supplies have
separate package pin assignments. For the same reason, GND and GNDQ also have separate pin
assignments.
The VMV and V_CCI pins must be shorted to each other on the board. Also, the GND and GNDQ pins
must be shorted to each other on the board. This will prevent unwanted current draw from the
power supply.
SSOs can cause signal integrity problems on adjacent signals that are not part of the SSO bus. Both
inductive and capacitive coupling parasitics of bond wires inside packages and of traces on PCBs
will transfer noise from SSO busses onto signals adjacent to those busses. Additionally, SSOs can
produce ground bounce noise and V_CCI dip noise. These two noise types are caused by rapidly
changing currents through GND and V_CCI package pin inductances during switching activities (EQ 2
and EQ 3).
Ground bounce noise voltage = L(GND) × di/dt
EQ 2
V_CCI dip noise voltage = L(V_CCI) × di/dt
EQ 3
Any group of four or more input pins switching on the same clock edge is considered an SSO bus.
The shielding should be done both on the board and inside the package unless otherwise
described.
In-package shielding can be achieved in several ways; the required shielding will vary depending
on whether pins next to the SSO bus are LVTTL/LVCMOS inputs, LVTTL/LVCMOS outputs, or
GTL/SSTL/HSTL/LVDS/LVPECL inputs and outputs. Board traces in the vicinity of the SSO bus have to
be adequately shielded from mutual coupling and inductive noise that can be generated by the
SSO bus. Also, noise generated by the SSO bus needs to be reduced inside the package.
PCBs perform an important function in feeding stable supply voltages to the IC and, at the same
time, maintaining signal integrity between devices.
Key issues that need to be considered are as follows:
• Power and ground plane design and decoupling network design
• Transmission line reflections and terminations
For extensive data per package on the SSO and PCB issues, refer to the ProASIC3/E SSO and Pin
Placement and Guidelines chapter of the handbook.
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