PROASIC3E Datasheet, PDF (35/37 Pages) Actel Corporation – I/O Structures in IGLOOe and ProASIC3E Devices

I/O Structures in IGLOOe and Pro ASIC3E Devices
Power-Up Behavior
Low-power flash devices are power-up/-down friendly; i.e., no particular sequencing is required for
power-up and power-down. This eliminates extra board components for power-up sequencing,
such as a power-up sequencer.
During power-up, all I/Os are tristated, irrespective of I/O macro type (input buffers, output buffers,
I/O buffers with weak pull-ups or weak pull-downs, etc.). Once I/Os become activated, they are set
to the user-selected I/O macros. Refer to the Power-Up/-Down Behavior of Low-Power Flash Devices
chapter of the ProASIC3 and ProASIC3E handbooks for details.
Drive Strength
Low-power flash devices have up to seven programmable output drive strengths. The user can
select the drive strength of a particular output in the I/O Attribute Editor or can instantiate a
specialized I/O macro, such as OUTBUF_S_12 (slew = low, out_drive = 12 mA).
The maximum available drive strength is 24 mA per I/O. Though no I/O should be forced to source
or sink more than 24 mA indefinitely, I/Os may handle a higher amount of current (refer to the
device IBIS model for maximum source/sink current) during signal transition (AC current). Every
device package has its own power dissipation limit; hence, power calculation must be performed
accurately to determine how much current can be tolerated per I/O within that limit.
I/O Interfacing
Low-power flash devices are 5 V–input– and 5 V–output–tolerant without adding any extra
circuitry. Along with other low-voltage I/O macros, this 5 V tolerance makes these devices suitable
for many types of board component interfacing.
Table 19 shows some high-level interfacing examples using low-power flash devices.
Table 19 • High-Level Interface Examples
Clock
I/O
Interface
Type
Frequency
Type Signals In
Signals Out Data I/O
GM
Src Sync
125 MHz
LVTTL
8
8
125 Mbps
TBI
Src Sync
125 MHz
LVTTL
10
10
125 Mbps
XSBI
Src Sync
644 MHz
LVDS
16
16
644 Mbps
XGMI
FlexBus 3
Pos-PHY3/SPI-3
Src Sync DDR
Sys Sync
Sys Sync
156 MHz
104 MHz
104
HSTL1
LVTTL
LVTTL
32
≤ 32
8,16,32
32
≤ 32
8,16,32
312 Mbps
≤ 104
≤ 104 Mbps
FlexBus 4/SPI-4.1
Pos-PHY4/SPI-4.2
Src Sync
Src Sync DDR
200 MHz
≥ 311 MHz
HSTL1
LVDS
16,64
16
16,64
16
200 Mbps
≥ 622 Mbps
SFI-4.1
CSIX L1
Hyper Transport
Rapid I/O Parallel
Src Sync
Sys Sync
Sys Sync DDR
Sys Sync DDR
622 MHz
≤ 250 MHz
≤ 800 MHz
250 MHz – 1 GHz
LVDS
HSTL1
LVDS
LVDS
16
32,64,96,128
2,4,8,16
8,16
16
32,64,96,128
2,4,8,16
8,16
622 Mbps
≤ 250 Mbps
≤ 1.6 Gbps
≤ 2 Gbps
Star Fabric
CDR
LVDS
4
4
622 Mbps
Note: Sys Sync = System Synchronous Clocking, Src Sync = Source Synchronous Clocking, and CDR = Clock and
Data Recovery.
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