PROASIC3E Datasheet, PDF (33/37 Pages) Actel Corporation – I/O Structures in IGLOOe and ProASIC3E Devices

I/O Structures in IGLOOe and Pro ASIC3E Devices
IGLOOe and ProASIC3E
Due to the comprehensive and flexible nature of IGLOOe and ProASIC3E device user I/Os, a naming
scheme is used to show the details of each I/O (Figure 20 on page 34). The name identifies to which
I/O bank it belongs, as well as the pairing and pin polarity for differential I/Os.
I/O Nomenclature = FF/Gmn/IOuxwByVz
Gmn is only used for I/Os that also have CCC access—i.e., global pins.
FF = Indicates the I/O dedicated for the Flash*Freeze mode activation pin in IGLOOe only
G = Global
m = Global pin location associated with each CCC on the device: A (northwest corner), B
(northeast corner), C (east middle), D (southeast corner), E (southwest corner), and F (west
middle)
n = Global input MUX and pin number of the associated Global location m, either A0, A1, A2, B0,
B1, B2, C0, C1, or C2. Refer to Global Resources in Actel Low-Power Flash Devices for
information about the three input pins per clock source MUX at CCC location m.
u = I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding in a
clockwise direction
x = P (Positive) or N (Negative) for differential pairs, or R (Regular—single-ended) for the I/Os
that support single-ended and voltage-referenced I/O standards only
w = D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the
pair are bonded out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if
both members of the pair are bonded out but do not meet the adjacency requirement; or S
(Single-Ended) if the I/O pair is not bonded out. For Differential (D) pairs, adjacency for ball
grid packages means only vertical or horizontal. Diagonal adjacency does not meet the
requirements for a true differential pair.
B = Bank
y = Bank number (0–7). The bank number starts at 0 from the northwest I/O bank and proceeds
in a clockwise direction.
V = V_REF
z = V_REF minibank number (0–4). A given voltage-referenced signal spans 16 pins (typically) in an
I/O bank. Voltage banks may have multiple V_REF minibanks.
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