Z86017 Datasheet, PDF (98/138 Pages) Zilog, Inc. – PCMCIA Interface Solution

Z86017/Z16017 PCMCIA Interface Solution
Product Specification
84
EEPROM Register
Address: SELECT 1Fh
Name: PCMCIA I/O Event Indication CCR4
Type: Read/Write
Table 68. PCMCIA I/O Event Indication CCR4: Address 1Fh
Bit Placement Bit Name
Bit 7
RSVDEVT3
Bit 6
RSVDEVT2
Bit 5
PIEvt
Bit 4
RIEvt
Description
Input pin EXTP_STSCHG/RES2 sets this bit. When
this bit is set and the PIEnab bit is set to 1, the
changed bit in the Card configuration and status
register is also set to 1.
Input pin ATA_DATA8/RES1 sets this bit. When this
bit is set and the PIEnab bit is set to 1, the changed
bit in the Card configuration and status register is
also set to 1.
The card latches this bit to a 1on receipt of a
validated incoming packet over an RF channel. The
source of this signal is ATA_DATA9/PACK_IN.
When this bit is set to 1 and the PIEnab bit is set to 1,
the changed bit in the Card configuration and status
register is also set to 1. And, if the SIGCHG bit in the
card configuration status register has also been set by
the host, the STSCHG pin (pin 63) goes Low. The
host writing a 1 to this bit clears it to 0. Writing a 0 to
this bit has no effect.
This bit is latched to a 1 by the card after the receipt
of a 1 on the ATA/PDIAG/ATA_BHE/RING-IN
signal. When this bit is set to 1 and the RIEnab bit is
set to 1, the changed bit in the Card configuration
and status register is also set to 1. And, if the
SIGCHG bit in the card configuration status register
has also been set by the host, then the STSCHG pin
(pin 63) goes Low. The host writing a 1 to this bit
clears it to 0. Writing a 0 to this bit has no effect.
PS012002-1201
Configuration Registers