Z86017 Datasheet, PDF (82/138 Pages) Zilog, Inc. – PCMCIA Interface Solution

Z86017/Z16017 PCMCIA Interface Solution
Product Specification
68
EEPROM Register
Address: SELECT 28h
Name: ATA/IDE Dual Drive Control
Type: Read/Write
Bit Placement Bit Name
Bit 0
M_S_enable
Bit 1
Drive_select
Bit 7-2
Reserved
NOTES:
1. Read Back Values: Z86017 00010000b = 10h
Z16017 00100000b = 20h
Description
This bit enables the Master/Slave mode control. When
this bit is set to 1, the Master/Slave function is enabled.
When it is set to 0, this function is disabled.
When programmed, this bit determines when to drive the
ATA/IDE bus. When set to 1, the ZX6017 drives the
ATA bus when the host writes a 1 into Bit 4 of the
“Drive/Head” task file register. Both primary and
secondary addresses are compared. If this bit is set to 0,
then the ZX6017 drives the bus if the host writes a 0 into
Bit 4 of the “Drive/Head” task fie register.¹
Unused
EEPROM Register
Address: SELECT 2Ah
Name: Power Management Timer Count Value
Type: Read/Write
Table 52. Power Management Timer Count Value: Address 2Ah
Bit Placement Bit Name
Bit 7-0
TIMER_VAL
Description
Power management timer count value. The timer reset
during all PCMCIA activity. When the timer expires, it
powers down all noncritical signals. TIMER intervals
(sec.) = PC_MCLK (sec.) * 2(27) * timer_val. For
example: PC_MCLK (20 MHz, 50 ns) * 2(27) * 1 = 6.67
sec. Also see Register 2Ch (Table 56).
PS012002-1201
Programming Internal Registers