Z86017 Datasheet, PDF (89/138 Pages) Zilog, Inc. – PCMCIA Interface Solution

Z86017/Z16017 PCMCIA Interface Solution
Product Specification
75
Table 58. Bus Control Register: Address 2Fh (Continued)
Bit Placement Bit Name
Bit 3
EN_MAP_IO_MEM
Bit 5-4
Bit 7-6
DUECE_WIDTH
DUECE_ACCESS_DLY
Description
When this bit is set, all memory accesses are mapped to
ATA_HIOR and ATA_HIOW. When it is cleared, all
memory accesses are mapped to ATA_MRD and
ATA_MWR.
These bits set the ATA_HIOR/HIOW strobe width and are
clocked by PC_MCLK_IN /2. At Power-On Reset, they
default to 00.
These bits set the ATA_HIOR/HIOW access delay and are
clocked by PC_MCLK_IN /2. At Power-On Reset, they
default to 00.
The ATA_HIOR/HIOW strobe width is three cycles minimum
(PC_MCLK_IN /2), plus IOCHRDY time (if any), plus width count
programmed in bits 5, 4 (Table 59).
Table 59. Strobe Width and Access Delay¹
Bits
765
4 Delay
000
000
001
001
010
010
011
011
00
10
00
10
01
11
01
11
NOTES:
1. Each count equals PC_MCLK_IN /2.
Width
0
1
2
3
0
1
2
3
765
100
100
101
101
110
110
111
111
Bits
4 Delay
02
12
02
12
03
13
03
13
Width
0
1
2
3
0
1
2
3
Programming Internal Registers
PS012002-1201