Z86017 Datasheet, PDF (17/138 Pages) Zilog, Inc. – PCMCIA Interface Solution

Z86017/Z16017 PCMCIA Interface Solution
Product Specification
3
PCMCIA
Interface
PC_A[25:11]
Address
Decoder
PCMCIA
Configuration
Registers
Window
Decoder
PCMCIA
Memory
and I/O
(16-Bit)
Peripheral Bus
Interface
(16-Bit)
Attribute Memory
(256 Bytes)
Control
Registers
EEPROM
Sequencer
SPI
Control
ATA/IDE
or
Peripheral
Bus
Local Serial
EEPROM
µP
SPI Port
Figure 1. ZX6017 Functional Block Diagram
Power-On Reset
The ZX6017 defaults to the Memory Only interface as outlined in the
PCMCIA specification upon deassertion of Power-On Reset /POR). The
hardware sets Busy on the PC_RDY/BSY pin and then addresses the
EE_MASTER pin. If the EE_MASTER pin is unconnected or pulled
High, the ZX6017 serial interface defaults to the Master mode and an
external EEPROM is required. If this pin is pulled Low, the SLAVE mode
is selected and an external microprocessor is required to configure the
ZX6017 through the serial interface pins.
Next, the hardware addresses the PC_ATA//HOE pin. If the PC_ATA/
HOE pin is held Low for 40 clocks (PC_MCLK_IN) after POR
deassertion, the ZX6017 is enabled for ATA/IDE to ATA/IDE
PASSTHROUGH mode. The PASSTHROUGH mode is for systems that
PCMCIA Interface Overview
PS012002-1201