Z86017 Datasheet, PDF (50/138 Pages) Zilog, Inc. – PCMCIA Interface Solution

Z86017/Z16017 PCMCIA Interface Solution
Product Specification
36
EEPROM REGISTER
EEPROM Register
Address: SELECT 00h
Name: Interface Configuration Register 0
Type: Read/Write
Table 11. Interface Configuration Register: Address 00h
Bit Placement Bit Name
Bits 1–0
Set Internal
Description
Internal Clock Divider. On Power-On Reset, clock divide-
by-32 selects the Master Clock. On Power-On Reset, set
these bits to 0 0. Table 12 describes Master Clock
Settings.
Bits 3–2
EN_OVERIDE
Bit 1
0
1
1
1
Bit 0
0 Slowest Clock, Clock In divide-by-32
1 Clock In divide-by-16
0 Clock In divide-by-4
1 Clock In
Overrides PCMCIA ATA mode bits, /PC_ATA//HOE
selection on the PCMCIA interface. On Power-On Reset,
both bits are set to 0. Sample /PC_ATA//HOE.
Bit 3
0
0
1
1
Bit 2
0 PC_ATA/HOE Sampled to Set Mode
1 Forces ATA/IDE Pass Through Mode
0 Forces PCMCIA Mode
1 Reserved
PS012002-1201
Programming Internal Registers