Z86017 Datasheet, PDF (52/138 Pages) Zilog, Inc. – PCMCIA Interface Solution

Z86017/Z16017 PCMCIA Interface Solution
Product Specification
38
Table 12. Master Clock
Register 0
Bit 1
Register 0
Bit 9
Clock In
EEPROM
CLK
Timing
Interrupt
Pulse¹Width Comments
0
0
50 ns
6.4 µs
204 µs
0
1
50 ns
3.2 µs
102 µs
1
0
50 ns
800 ns
25 µs
Recommended
1
1
50 ns
200 ns
5.25 µs
0
0
100 ns
12.8 µs
404 µs
0
1
100 ns
6.4 µs
204 µs
1
0
100 ns
1.6 µs
50 µs
1
1
100 ns
400 ns
12.5 µs
Recommended
NOTES:
1. The pulse width of the /PC.IREQ signal in pulse mode is dependent on the clock period of the master clock input (TPMCKIN). The pulse
width of the /PC.IREQ signal is equal to 192 x TPMCKIN.
PS012002-1201
Programming Internal Registers