Z85C3010VSG Datasheet, PDF (9/83 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
1
Overview
The features of Zilog’s Z80C30 and Z85C30 devices include:
• Z85C30: optimized for nonmultiplexed bus microprocessors
• Z80C30: optimized for multiplexed bus microprocessors
• Pin-compatible to NMOS versions
• Two independent 0 to 4.1Mbps, full-duplex channels, each with separate crystal oscil-
lator, Baud Rate Generator (BRG), and Digital Phase-Locked Loop (DPLL) for clock
recovery
• Multiprotocol operation under program control; programmable for NRZ, NRZI or FM
data encoding
• Asynchronous Mode with 5 to 8 bits and 1, 1½, or 2 stop bits per character, program-
mable clock factor, break detection and generation; parity, overrun, and framing error
detection
• Synchronous Mode with internal or external character synchronization on 1 or 2 syn-
chronous characters and CRC generation and checking with CRC-16 or CRC-CCITT
preset to either 1s or 0s
• SDLC/HDLC Mode with comprehensive frame-level control, automatic zero insertion
and deletion, I-Field residue handling, abort generation and detection, CRC generation
and checking, and SDLC loop
• Software interrupt acknowledge feature (not available with NMOS)
• Local Loopback and Auto Echo modes
• Supports T1 Digital Trunk2
• Enhanced DMA support (not available with NMOS), 10 x 19-bit status FIFO, 14-bit
byte counter
• Speeds
– Z85C3O: 8.5, 10, 16.384MHz
– Z80C3O: 8, 10MHz
Other Features for Z85C30 Only
Some of the features listed below are available by default. Some of them (features with *)
are disabled on default to maintain compatibility with the existing Serial Communications
Controller (SCC) design, and program to enable through WR7:
PS011707-1013
Overview