Z85C3010VSG Datasheet, PDF (39/83 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
31
Frame Status FIFO Circuitry
RR1
SCC Status Reg
Residue Bits (3)
Overrun, CRC Error
Byte Counter
5 Bits
14 Bits
FIFO Array
10 Deep by 19 Bits Wide
Reset on Flag Detect
Increment on Byte Detection
Enable Count in SDLC
End of Frame Signal
Status Read Comp
Tail Pointer
4-Bit Counter
Head Pointer
4-Bit Counter
5 Bits
EOF = 1
6 Bits 8 Bits
4-Bit Comparator
Over
Equal
6-Bit MUX
EN
2 Bits
6 Bits
RR1
Bit 7 Bit 6 Bits 5-0
RR6
FIFO Enable
Interface
to SCC
RR7 D5-D0 + RR6 D7-D0
Byte Counter Contains 14 bits
for a 16 KByte maximum count
RR7 D6
FIFO Data available status bit Status Bit set to 1
When reading from FIFO
WR(15) Bit 2
Set Enables
Status FIFO
RR7 D7
FIFO Overflow Status Bit
MSB pf RR(7) is set on Status FIFO overflow
In SDLC Mode the following definitions apply
Figure 13. SDLC Frame Status FIFO
The sequence for operation of the byte count and FIFO logic is to read the registers in the
following order. RR7, RR6, and RR1 (reading RR6 is optional). Additional logic prevents
the FIFO from being emptied by multiple reads from RR1. The read from RR7 latches the
FIFO empty/full status bit (D6) and steers the status multiplexer to read from the SCC
megacell instead of the status FIFO (since the status FIFO is empty). The read from RR1
PS011707-1013
Functional Descriptions