Z85C3010VSG Datasheet, PDF (46/83 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
38
Read Registers
The SCC contains ten read registers (eleven, counting the receive buffer (RR8) in each
channel). Four of these can be read to obtain status information (RR0, RR1, RR10, and
RR15). Two registers (RR12 and RR13) are read to learn the Baud Rate Generator time
constant. RR2 contains either the unmodified interrupt vector (Channel A) or the vector
modified by status information (Channel B). RR3 contains the Interrupt Pending (IP) bits
(Channel A only; see Figure 19). RR6 and RR7 contain the information in the SDLC
Frame Status FIFO, but is only read when WR15 D2 is set (see Figures 19 and 20).
PS011707-1013
Functional Descriptions