Z85C3010VSG Datasheet, PDF (53/83 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
45
AS
CS0
INTACK
AD7–AD0
R/W
CS1
Address
Data
DS
Figure 25. Write Cycle Timing
Interrupt Acknowledge Cycle Timing
Figure 26 shows the Interrupt Acknowledge cycle timing. The address on AD7–AD0 and
the state of CS0 and INTACK are latched by the rising edge of AS. If INTACK is Low, the
address and CS0 are ignored. The state of the R/W and CS1 are also ignored for the dura-
tion of the Interrupt Acknowledge cycle. Between the rising edge of AS and the falling
edge of DS, the internal and external IEI/IEO daisy chains settle. If there is an interrupt
pending in the SCC, and IEI is High when DS falls, the Acknowledge cycle was intended
for the SCC. In this case, the SCC is programmed to respond to RD Low by placing its
interrupt vector on D7-D0 and internally setting the appropriate Interrupt-Under-Service
latch.
PS011707-1013
Functional Descriptions