Z85C3010VSG Datasheet, PDF (41/83 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
33
Z80C30
All SCC registers are directly addressable. A command issued in WR0B controls how the
SCC decodes the address placed on the address/data bus at the beginning of a read or write
cycle. In the Shift Right Mode, the channel select A/B is taken from AD0 and the state of
AD5 is ignored. In the Shift Left Mode, the channel select A/B is taken from AD5 and the
state of AD0 is ignored. AD7 and AD6 are always ignored as address bits and the register
address occupies AD4-AD1.
Z85C30/Z80C30 Setup
The system program first issues a series of commands to initialize the basic mode of oper-
ation. This is followed by other commands to qualify conditions within the selected mode.
For example, in Asynchronous Mode, character length, clock rate, number of stop bits,
and even or odd parity must be set first. The interrupt mode is set, and finally, the receiver
and transmitter are enabled.
Write Registers
The SCC contains 15 write registers for the 80C30, while there are 16 for the 85C30 (one
more additional write register if counting the transmit buffer) in each channel. These write
registers are programmed separately to configure the functional ‘personality’ of the chan-
nels. There are two registers (WR2 and WR9) shared by the two channels that are
accessed through either of them. WR2 contains the interrupt vector for both channels,
while WR9 contains the interrupt control bits and reset commands. Figures 15 through 18
show the format of each write register.
PS011707-1013
Functional Descriptions