Z85C3010VSG Datasheet, PDF (49/83 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
41
Read Cycle Timing
Figure 21 shows read cycle timing. Addresses on A/ B and D/C and the status on INTACK
must remain stable throughout the cycle. If CE falls after RD falls, or if CE rises before
RD rises, the effective RD is shortened.
A/B, D/C
Address Valid
INTACK
CE
RD
D7–D0
Data Valid
Figure 21. Read Cycle Timing
PS011707-1013
Functional Descriptions